To develop and implement hardware accelerators for Post-Quantum Cryptography (PQC) algorithms using Hardware Description Languages (HDLs) such as Verilog/SystemVerilog and VHDL. Utilize advanced FPGA and EDA tools for simulation, verification, synthesis, and performance evaluation of cryptographic hardware architectures including CRYSTALS-Kyber (ML-KEM) and CRYSTALS-Dilithium (ML-DSA). Contribute to FPGA prototyping, CMOS-compatible soft IP development, security validation, technical documentation, and research publications related to hardware cybersecurity and semiconductor IP design.

i. Design and develop FPGA-based hardware accelerators for Post-Quantum Cryptography applications including CRYSTALS-Kyber and CRYSTALS-Dilithium.
ii. Perform HDL simulation, functional verification, synthesis, timing analysis, and hardware testing using FPGA and EDA tools.
iii. Support development of CMOS-compatible synthesizable soft IP including RTL optimization, verification, and ASIC design flow activities.
iv. Develop and validate cryptographic modules such as NTT engines, SHAKE hash cores, TRNG units, and modular arithmetic architectures.
v. Assist in benchmarking hardware performance including throughput, area, timing, and power analysis.
vi. Support security validation activities including side-channel analysis awareness, entropy validation, and NIST test vector verification.
vii. Prepare technical documentation, research reports, conference papers, and journal publications related to PQC hardware acceleration and semiconductor security.
 

i. Strong concepts in digital design, computer architecture, and Hardware Description Languages (HDLs) such as Verilog, SystemVerilog, or VHDL.
ii. Experience in FPGA-based design implementation, simulation, and verification using EDA tools.
iii. Experience in writing technical reports and research articles.
iv. Knowledge or experience in cryptographic hardware, embedded systems, or hardware security will be an added advantage.
v. Work experience in research grants and semiconductor/FPGA projects will have added advantage.
 

i. Knowledge in combinational and sequential digital circuit design.
ii. Ability to perform timing and functional simulations using FPGA and EDA tools such as ModelSim, Questa, Vivado, or Quartus.
iii. Ability to implement and verify designs on FPGA hardware platforms.
iv. Knowledge of FPGA architecture, RTL design, and hardware optimization techniques including pipelining and parallel processing.
v. Familiarity with ASIC/CMOS design flow, synthesis, static timing analysis, and hardware verification will be an advantage.
vi. Knowledge of cybersecurity hardware concepts, cryptographic accelerators, or Post-Quantum Cryptography will be an added advantage
 

Master’s or Ph.D. degree in Electronics, Electrical, or Computer Engineering